The present invention relates to a cell delineation method and a cell delineation circuit and, more particularly, to a cell delineation method and a cell delineation circuit for establishing a cell delineation by using a point that a certain information block in a cell satisfies a CRC (Cyclic Redundancy Check) rule.
In the case of establishing a cell delineation in a fixed length packet communication, there is a method of establishing the cell delineation by using a point that a certain information block in the cell satisfies the CRC (Cyclic Redundancy Check) rule.
According to the CCITT (International Telegraph and Telephone Consulative Committee), there is shown a method of establishing the cell delineation by using a point that an information block of five bytes from the head of an ATM (Asynchronous Transfer Mode) cell satisfies the CRC rule with respect to the cell delineation of the ATM signal.
A cell delineation circuit using the CRC is characterized in that a CRC calculator is used as a SYNC pattern detector. The CRC calculator is as shown in FIG. 2 in the case where a generator polynomial is expressed by X.sup.8 +X.sup.2 +X+1. According to the CRC calculator, after all of flip-flop circuits 302-1 to 302-8 were reset to 0 at the beginning of calculations, 40 bits are input and, thereafter, the results of the calculations are generated to outputs of the eight flip-flop circuits 302-1 to 302-8 in the case of the ATM cell. In FIG. 2, reference numerals 301-1 to 301-3 denote exclusive-OR.
An example of a construction of the cell delineation circuit in the ATM cell has been described in Toshima and Takino, "Design of Cell Delineation Circuit Using Header Error Control Bits", IEICEJ Technical Report, SC-89-70, November, 1989.
FIGS. 3 and 4 show examples of construction of the cell delineation circuits which have been adapted to the case where a signal speed is high, which examples have been shown in the above-mentioned literature. In FIG. 3, an input signal 101 is converted into parallel signals of eight bits by a serial to parallel converter 1. In order to execute a phase alignment, seven bits among the eight bits are delayed by a delay circuit 2. Thus, resultant parallel signals of fifteen bits are supplied to a shift matrix 201. Parallel output signals of eight bits of the shift matrix 201 are converted into parallel signals of 40 bits by registers 202-1 to 202-4 and are supplied to a CRC calculator 3' for executing calculations, which are feedback loop, in a lump by using logic circuits which are formed to have multiple stages. The results of the CRC calculations are latched and are checked by a zero-detector 4 to see if they satisfy the CRC rule or not. The results of the discriminations are given to a protection circuit 9'. If the CRC rule is continuously satisfied a few times, the cell delineation is established. After the cell delineation has been established, if the CRC rule is subsequently not continuously satisfied a few times, it is determined that a loss of delineation occurred. On the other hand, although all of the patterns were inspected by the phase which is at present being inspected, if the results of the discriminations do not satisfy that CRC rule, a phase alignment is performed by the shift matrix 201 by a signal from a phase alignment controller. By executing the phase alignment, a process is performed by checking whether the CRC coding law is respected for the assumed header field with respect to all of the patterns. A calculation timing generator 5' first starts a CRC coding law checking every eight bits and outputs a control signal for inspection of every cell once an agreement is found.
In FIG. 4, the input signal 101 is converted into the parallel signals of eight bits by the serial to parallel converter 1 and further converted into the parallel signals of 48 bits by registers 205-1 to 205-5. The parallel signals of 48 bits are, moreover, converted into eight series, each of which is a wide parallel signal 40 bits. Each of these series are shifted one bit by one bit from each other. In a manner similar to the case of FIG. 3, the 40-bit parallel signals of the eight series are subjected to calculations of CRC and checks are made to see if they satisfy the CRC rule or not, thereby establishing the cell delineation. However, in the case of FIG. 4, since the CRC calculations are executed in a lump for the signals of eight series having different phases, the phase alignment control as in FIG. 3 is unnecessary and checks of CRC can be performed with respect to all of the patterns. In FIG. 4, reference numerals 3'-1 to 3'-8 denote CRC calculators; 203-1 to 203-8 indicate registers; 4-1 to 4-8 zero-detectors; and 9'-1 to 9'-8 protection circuits.
In the cell delineation circuit of FIG. 3, in order to set the correct phase so as to establish the cell delineation, it is necessary to count the number of pattern mismatch times and align the word phase in accordance with the result of the count value. In the circuit shown in the diagram, in the case where the phase of parallel output signals were aligned, the number of bits to be processed by the CRC is so large to be 40 bits. Therefore, there are problems such that a phase deviation between such bits and the remaining bits in a register occurs, and the result of the calculation of the CRC cannot be used just after completion of the phase alignment. In addition, a delineation acquisition time also increases due to such a phase alignment.
On the other hand, in FIG. 4, the CRC coding law checking result can be obtained bit-by-bit by arranging eight CRC calculators 3'-1 to 3'-8 in parallel. However, there are problems such that as circuits other than the serial to parallel converter, register, shift matrix, and timing generator, it is necessary to use as many circuits as the number of parallel development multiple of the serial to parallel converter. In other words, in the example of FIG. 4, eight CRC calculators, eight zero detectors, etc., are required, thereby greatly increasing the necessary amount of hardware.